1. Field of the Invention
The present invention relates to a bus clock rate adjusting method, more particularly to a dynamic bus clock rate adjusting method for dynamically adjusting an operating clock rate of a bus according to a working clock rate of a slave device to be accessed.
2. Description of the Related Art
Referring to FIG. 1, a bus 10 of a computer system, such as a System Management Bus (SMBus) or an Inter-Integrated Circuit (I2C) bus, is provided to be electrically coupled with a plurality of slave devices, such as an Electrically Erasable Programmable Read-Only Memory (EEPROM) 11, an embedded controller (or a keyboard controller) 12, and a High Definition Multimedia Interface (HDMI) transceiver 13. Moreover, a bus controller 14, such as a SMBus controller or an I2C bus controller, is coupled electrically to the bus 10, so as to decide an operating clock rate of the bus 10 and to access or perform setting operations on the slave devices 12, 13 and 14 via the bus 10.
Owing to the characteristics of the SMBus and the I2C bus, a device which operates at a lower working clock rate, such as the embedded controller (or the keyboard controller) 12 with a working clock rate ranging from 10 KHz to 100 KHz, is incapable of working on a bus with a higher operating clock rate. While a device which operates at a higher working clock rate, such as the HDMI transceiver 13 with a highest working clock rate of 400 KHz, is capable of working on a bus with a lower operating clock rate. Based on the aforementioned limitations, conventionally, a central processing unit (CPU) 15 is configured to set the bus controller 14 such that the operating clock rate of the bus 10 is set to a working clock rate at which the slowest slave device operates, such as the highest working clock rate at which the embedded controller (or the keyboard controller) 12 operates, i.e., 100 KHz.
Furthermore, since the aforementioned EEPROM 11 is only accessed by the CPU 15 during a booting process, and the HDMI transceiver 13 is only required to transmit a control signal via the bus 10 when an external display device (not shown) is connected thereto, for most of the time, the bus 10 is primarily used for reading of a scan code of a keyboard temporarily stored in the embedded controller (or the keyboard controller) 12. Moreover, it is favorable in terms of power saving for the bus 10 to operate at a lower operating clock rate. Therefore, taking power saving into consideration, the operating clock rate of the bus 10 should be set to the lowest working clock rate of the embedded controller (or the keyboard controller) 12, i.e., 10 KHz.
Nevertheless, in this way, since the EEPROM 11 may not be accessed at a higher clock rate, booting efficiency is limited by the operating clock rate of the bus 10. Moreover, efficiency of the HDMI transceiver 13 when connected with the external display device would also be limited by the operating clock rate of the bus 10, such that the external display device may not display images timely.